    .arm
    .syntax unified
    .cpu cortex-a7
    
    .equ  OS_SPSR_SYS_MODE, 0x1F
    .global   _estack
_estack:
     .size   _estack, . - _estack

     .global   _irqstack
_irqstack:
     .size   _irqstack, . - _irqstack

    .section .vectors ,"ax" 
    .align 5
   .global Reset_Handler 
   .extern bss_clear_loop
   .global _start
_start:
    ldr pc, =Reset_Handler 
    ldr pc, =Undefined_Handler
    ldr pc, =SVC_Handler
    ldr pc, =PrefetchAbort_Handler
    ldr pc, =DataAbort_Handler
    ldr pc, =Reserved_Handler
    ldr pc, =IRQ_Handler
    ldr pc, =FIQ_Handler

    .section .text
    .global archOsStart
    .extern SVC_Handler
    .global __bss_start
    .global __bss_end
    .global context_switch
    .global IRQ_Handler
    .global Undefined_Handler
    .global PrefetchAbort_Handler
    .global DataAbort_Handler
    .global Reserved_Handler
    .global FIQ_Handler
    .global osScheduleTaskSw
    .global exception_handler
    .global archOsStart
    .global gic_irq_handler
    .global tringSvcHandler
    .code 32

.macro disable_icache
    MRC p15, 0, r0, c1, c0, 0

    BIC r0, r0, #(1 << 12)
    BIC r0, r0, #(1 << 2)

    MCR p15, 0, r0, c1, c0, 0
.endm
.macro enbale_icache
     mov r0, #0
    mcr p15, 0, r0, c7, c5, 0   @ ICIALLU
    dsb
    isb
    mrc p15, 0, r0, c1, c0, 0  
    orr r0, r0, #(1 << 12)     
    mcr p15, 0, r0, c1, c0, 0 
    MOV R0, #0
    MCR p15, 0, R0, c7, c5, 0 
    isb                        
.endm




    .align 3
Reset_Handler:
    /*** IRQ sp register stack *****/ 
    mrs r0, cpsr 
    bic r0, r0, #0x1f
    orr r0, r0, #0x12
    msr cpsr, r0
    ldr sp, =_irqstack
    /** abort sp register starck **/
    mrs r0, cpsr 
    bic r0, r0, #0x1f
    orr r0, r0, #0x17
    msr cpsr, r0
    ldr sp, =_irqstack
  
    /** abort sp register starck **/
    mrs r0, cpsr 
    bic r0, r0, #0x1f
    orr r0, r0, #0x1B
    msr cpsr, r0
    ldr sp, =_irqstack



    /*** SVC sp register stack ****/
    bic r0, r0, #0x1f
    orr r0, r0, #0x13
    msr cpsr, r0
    ldr sp, =_estack

    ldr r0, = __bss_start 
    ldr r1, = __bss_end
    subs r2, r1, r0
    beq bss_clear_done

    mov r3, #0
bss_clear_loop:
    str r3, [r0], #4
    subs r2, r2, #4
    bne bss_clear_loop 

bss_clear_done:
    bl  main
    b .
 
SVC_Handler:
    stmfd   sp!,{r0-r12,lr} 
    CPSID   if
    mrs     r0, cpsr
    stmfd   sp!, {r0}
    bl      osScheduleTaskSw 
    CPSIE   if
    cmp     r0, #0
    beq     1f
    ldr     r0, =g_osTask   /* r0 = &g_osTask */
    ldr     r1, [r0]        /* r1 = &g_osTask.taskRun*/
    str     sp, [r1]

    ldr     r2, [r0, #4] /* r2 = &g_osTask.taskNew */
    str     r2, [r0]    /*  g_osTask.taskRun = g_osTask.taskNew*/
    ldr     sp, [r2]     /* sp = &g_osTask.taskNew->stackPoint */
1:    
    ldmfd   sp!,{r0}
    and     r0, r0, #OS_SPSR_SYS_MODE
    cmp     r0, #OS_SPSR_SYS_MODE
    beq     2f
    ldmfd   sp!, {r0-r12,lr} 
    movs    pc, lr

2:
    movs    lr, sp
    ldmfd   lr, {r0-r13}
    add     lr, lr,#60
    ldmfd   lr!, {pc}



Undefined_Handler:
PrefetchAbort_Handler:
DataAbort_Handler:
Reserved_Handler:
FIQ_Handler:
    stmfd sp!, {r0-r12,lr}
    mrs r0, cpsr 
    stmfd sp!,{r0}
    movs r0 , sp

    bl exception_handler

IRQ_Handler: 
    sub     lr, lr, #4
    srsfd   sp!, #0x13
    cps     #0x13 
    stmfd sp!, {r0-r12, lr}            
    bl  gic_irq_handler
    movs   r0, #0x42
    bl  SVC_Handler
    ldmfd sp!, {r0-r12, lr}
    rfefd sp!
        

archOsStart:  
    ldr r0, =g_osTask
    ldr r1, [r0]
    ldr lr, [r1,#0]        /* g_osTask.taskRun->stackPoint */
    ldmfd lr!,{r0}

    ldmfd lr, {r0-r13}
    add   lr, lr,#60
    ldmfd lr!, {pc}
    b .

tringSvcHandler:
   stmfd    sp!,{r0-r12,lr}
   svc      #0x42
   nop
   ldmfd    sp!,{r0-r12,lr}
   movs     pc, lr

